ASIC Technical Leader- DFT

Cisco

San Jose, CA, United States
Full-time
Posted June 08, 2026

Job Description

The application window is expected to close on: 07/10/2026
**Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received** .

**Meet the Team:**

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

**Key Contributions:**

+ Manages the definition, architecture and design of high performance ASICs
+ Owns applications or multiple complex functional areas<...