SoC/IP Verification Engineer: UVM & Coverage

A leading technology company is seeking a hands-on SoC Design Verification Engineer in Guadalajara, Mexico. The role involves driving verification of complex SoC/IP blocks, from planning to execution. You will develop UVM testbench environments and collaborate cross-functionally to deliver high-quality silicon. Ideal candidates have a degree in Electrical Engineering, at least 5 years of experience in design verification, and strong skills in UVM/SystemVerilog, along with proficiency in English.
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